In current computer architectures, application bandwidth requirements are increasing exponentially. This is true for both memory and input/output (IO) subsystems. Also, recently it has been observed that supporting this exponential growth in bandwidth on existing interconnects has become increasingly difficult because of engineering as well as industry enabling challenges.
An example of this trend is seen in the available speeds of upcoming generations of the well-known Peripheral Component Interconnect Express (PCIe™) interconnect technology. Specifically, for the upcoming PCIe™ Generation (Gen) 3.0 signaling speed, it was desired that the bandwidth should be doubled from the current PCIe™ Gen 2.0 levels (5.0 giga transfers per second (GT/s)) in accordance with the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereinafter the PCIe™ Specification). However, because of engineering challenges, the industry compromised by adopting slower (8.0 GT/s vs. 10.0 GT/s) speeds and not performing 8 b/10 b encoding to achieve bandwidths close to 10.0 GT/s. Various techniques will be needed in enabling the technology to keep pace with industry bandwidth requirements.
One such technique is compression. Over the years, compression has been successfully used in a variety of interconnect systems. However, such known compression techniques can suffer from complexity and overhead costs that diminish their utility.